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Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U-[5/6]-B HYS72D64300[G/H]U-[5/6]-B HYS64D128320[G/H]U-[5/6]-B HYS72D128320[G/H]U-[5/6]-B
184-Pin Unbuffered Dual-In-Line Memory Modules UDIMM DDR SDRAM
Memory Products
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Edition 2004-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U-[5/6]-B HYS72D64300[G/H]U-[5/6]-B HYS64D128320[G/H]U-[5/6]-B HYS72D128320[G/H]U-[5/6]-B
184-Pin Unbuffered Dual-In-Line Memory Modules UDIMM DDR SDRAM
Memory Products
Never
stop
thinking.
HYS64D64300[G/H]U-[5/6]-B, HYS72D64300[G/H]U-[5/6]-B, HYS64D128320[G/H]U-[5/6]-B Revision History: Previous Version: Page 7 8,12ff 22,23 24,27,30,33 Rev. 1.0 Rev. 0.5 Subjects (major changes since last revision) Added Non-Green Modules DDR400 & DDR333 and removed DDR266 editorial changes Updated IDD currents to final Update SPD Codes 2004-05
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
5
Rev. 1.0, 2004-05
184-Pin Unbuffered Dual-In-Line Memory Modules UDIMM
HYS64D64300[G/H]U-[5/6]-B HYS72D64300[G/H]U-[5/6]-B HYS64D128320[G/H]U-[5/6]-B HYS72D128320[G/H]U-[5/6]-B
1
1.1
* * * * * * * * * * * * *
Overview
Features
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main memory applications One rank 64M x 64, 64M x72 and two ranks 128M x 64, 128M x72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (0.2V) power supply Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. Jedec standard reference layout Gold plated contacts DDR400 speed grade supported Lead-free
Table 1
Performance -5 Component Module @CL3 @CL2.5 @CL2 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz
Part Number Speed Code Speed Grade max. Clock Frequency
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
The HYS64D64300[G/H]U-[5/6]-B, HYS72D64300[G/H]U-[5/6]-B, HYS64D128320[G/H]U-[5/6]-B, and HYS72D128320[G/H]U-[5/6]-B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules (UDIMM) organized as 64M x64, 128M x64 for non-parity and 64M x72,128M x72 for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer
Data Sheet
6
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Overview Table 2 Type PC3200 (CL=3.0) HYS64D64300GU-5-B HYS72D64300GU-5-B HYS64D128320GU-5-B HYS72D128320GU-5-B PC2700 (CL=2.5) HYS64D64300GU-6-B HYS72D64300GU-6-B HYS64D128320GU-6-B HYS72D128320GU-6-B PC3200 (CL=3.0) HYS64D64300HU-5-B HYS72D64300HU-5-B HYS64D128320HU-5-B HYS72D128320HU-5-B PC2700 (CL=2.5) HYS64D64300HU-6-B HYS72D64300HU-6-B HYS64D128320HU-6-B HYS72D128320HU-6-B PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 512 MB DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 512 MB DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 512 MB DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 512 MB DIMM two ranks 1 GB DIMM two ranks 1 GB ECC-DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x8) Ordering Information Compliance Code Description SDRAM Technology
one rank 512 MB ECC-DIMM 512 Mbit (x8)
one rank 512 MB ECC-DIMM 512 Mbit (x8)
one rank 512 MB ECC-DIMM 512 Mbit (x8)
one rank 512 MB ECC-DIMM 512 Mbit (x8)
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3 Pin# Name 122 27 141 118 115 I NC I I I NC I I I I NC I I NC I I I I I I I I I I I I I SSTL - SSTL SSTL SSTL - SSTL SSTL SSTL SSTL - SSTL SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 8 Clock Signals 2:0 Note: For clock net loading see block diagram, CK0 is NC on 1R x16 Complement Clock Signals 2:0 Note: For clock net loading see block diagram, CK0 is NC on 1R x16 Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module NC Note: 1-rank module Chip Select Rank 0 Chip Select Rank 1 Note: 2-rank module NC Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Bank Address Bus 2:0 Address Bus 11:0 167 A8 A9 A10 AP A11 A12 Pin Configuration of UDIMM (cont'd) Pin Buffer Function Type Type I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC A13 NC I - SSTL Note: 128 Mbit module Note: 1 Gbit module NC NC - based Address Bus 11:0
The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Name Clock Signals 137 16 76 138 17 75 21 111 CK0 NC CK1 CK2 CK0 NC CK1 CK2 CKE0 CKE1 Pin Configuration of UDIMM Pin Buffer Function Type Type
Address Signal 13 based
Note: Module based on 512 Mbit or smaller dies Data Bus 63:0
Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Control Signals 157 158 S0 S1
154 65 63 59 52 48 43 41 130 37 32 125 29
RAS CAS WE BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7
Address Signals
Data Sheet
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration Table 3 Pin# Name 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 Pin Configuration of UDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL NC NC - 5 14 25 36 56 67 78 86 47 NC DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobe 8 Note: ECC type module Note: Non-ECC module 144 NC CB7 NC I/O - SSTL 142 NC CB6 NC I/O - SSTL 135 NC CB5 NC I/O - SSTL 134 NC CB4 NC I/O - SSTL 51 NC CB3 NC I/O - SSTL 49 NC CB2 NC I/O - SSTL 45 NC CB1 NC I/O - SSTL Data Bus 63:0 Table 3 Pin# Name 178 179 44 DQ62 DQ63 CB0 Pin Configuration of UDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O SSTL SSTL SSTL Check Bit 0 Note: ECC type module Note: Non-ECC module Check Bit 1 Note: ECC type module Note: Non-ECC module Check Bit 2 Note: ECC type module Note: Non-ECC module Check Bit 3 Note: ECC type module Note: Non-ECC module Check Bit 4 Note: ECC type module Note: Non-ECC module Check Bit 5 Note: ECC type module Note: Non-ECC module Check Bit 6 Note: ECC type module Note: Non-ECC module Check Bit 7 Note: ECC type module Note: Non-ECC module Data Strobe Bus 7:0 Note: See block diagram for corresponding DQ signals Data Bus 63:0
Data Sheet
9
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration Table 3 Pin# Name 97 107 119 129 149 159 169 177 140 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 NC EEPROM 92 91 181 182 183 1 184 SCL SDA SA0 SA1 SA2 I I/O I I I CMOS Serial Bus Clock OD Serial Bus Data CMOS Slave Address Select CMOS Bus 2:0 CMOS I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply NC 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 NC - Pin Configuration of UDIMM (cont'd) Pin Buffer Function Type Type I I I I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - Data Mask 8 Note: ECC type module Note: Non-ECC module Data Mask Bus 7:0 Table 3 Pin# Name 3, VSS 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 Other Pins 82 Pin Configuration of UDIMM (cont'd) Pin Buffer Function Type Type GND - Ground Plane
Power Supplies
VREF AI - VDDSPD PWR -
PWR -
VDDID
O
OD
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB Not connected Pins not connected on Infineon UDIMMs
15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 Data Sheet
PWR -
Power Supply
10
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4 I O I/O AI PWR GND NC
Abbreviations for Pin Type Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Table 5 SSTL LV-CMOS
Abbreviations for Buffer Type Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS
Abbreviation Description
Abbreviation Description
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
VREF DQS0 NC DQ09 CK1 CKE0 DQS2 A7 DQ24 A04 -
Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037
VSS VDD VSS VDDQ DQ10 DQ16 A9 DQ19 DQ25 DQ26 -
Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039
Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040
- DQ01 - DQ03 - DQ08 - CK1 - DQ11 - DQ17 - DQ18 - A5 - DQS3 - DQ27
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 -
DQ00 DQ02 NC DQS1 VSS VDDQ VSS VDDQ VSS VDD
A2 CB01/NC CB02/NC DQ32 DQ34 DQ40 CAS DQ43 DQ49 VDDQ VSS VDD VSS VSS DM0 NC DQ12 DQ14 NC DQ21 DQ22 A6 DM3 DQ31 CK0/NC A10/AP VSS DM4 DQ44 S0 DQ46 DQ52 DM6 NC DM7 SA0 -
Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181
A1 DQS8/NC CB03/NC DQ33 BA0 WE DQS5 NC CK2 DQ50 DQ56 DQ58 SDA DQ05 DQ07 NC DM1 CKE1/NC A12/NC DM2 DQ23 DQ29 DQ30 CB5/NC VSS VDDQ DQ37 DQ39 DQ45 DM5 NC A13/NC DQ55 DQ61 DQ63 SA2 -
Pin 043 Pin 047 Pin 051 Pin 055 Pin 059 Pin 063 Pin 067 Pin 071 Pin 075 Pin 079 Pin 083 Pin 087 Pin 091 Pin 095 Pin 099 Pin 103 Pin 107 Pin 111 Pin 115 Pin 119 Pin 123 Pin 127 Pin 131 Pin 135 Pin 139 Pin 143 Pin 147 Pin 151 Pin 155 Pin 159 Pin 163 Pin 167 Pin 171 Pin 175 Pin 179 Pin 183
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 -
CB00/NC A0 BA1 DQS4 DQ35 DQ41 DQ42 DQ48 CK2 DQ51 DQ57 DQ59 SCL VDDQ VSS VDDQ VDD VDDQ VSS VDD VSS VDDQ VSS VDDQ DM8/NC CB7/NC VDD VSS VDDQ VSS VDDQ VDD VDDQ VSS VDDQ VDDSPD
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 -
FRONTSIDE
BACKSIDE
VSS VDD VSS VDDQ VSS VDDQ VSS VDD VSS DQS6 VDDID DQS7 NC DQ04 DQ06 NC DQ13 DQ15 DQ20 A11 A8 DQ28 A3 CB4/NC CK0/NC CB06/NC DQ36 DQ38 RAS S1 /NC DQ47 DQ53 DQ54 DQ60 DQ62 SA1 MPPD0030
Figure 1 Data Sheet
Pin Configuration 184-Pin, UDIMM 11 Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
Table 6 Density 512 MB 512 MB 1 GB 1 GB
Address Format Organization 64M x64 64M x72 128M x64 128M x72 Memory Ranks 1 1 2 2 SDRAMs 64M x8 64M x8 64M x8 64M x8 # of SDRAMs 8 8 16 18 # of row/bank/ columns bits 13/2/11 13/2/11 13/2/12 13/2/12 Refresh 8K 8K 8K 8K Period 64 ms 64 ms 64 ms 64 ms Interval 7.8 s 7.8 s 7.8 s 7.8 s
BA0 - BA1 A0 - An RAS CAS WE CKE0 S0 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
BA0 - BA1: SDRAMs D0 - D7 A0 - An: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7
VDDSPD VDD/VDDQ VREF VSS VDDID
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D7 VREF: SDRAMs D0 - D7 VSS: SDRAMs D0 - D7 Strap: see Note 1 D3 D6
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
D4
D7
D2
D5
SCL SAD SA0 SA1 SA2 VSS
SCL SAD A0 A1 A2 WP
E0
MPBD1011
Figure 2 Note:
Block Diagram UDIMM Raw Card A x64, 1 Rank, x8
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 5.1 5 %
Table 7 Clock Input CK0, CK0 CK1, CK1 CK2, CK2
Clock Signal Loads Number of SDRAMs 2 SDRAMs 3 SDRAMs 3 SDRAMs Note -- -- --
Data Sheet
12
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 S0 S1 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
BA0 - BA1: SDRAMs D0 - D15 A0 - An: SDRAMs D0 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 WE: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 CKE:SDRAMs D8 - D15
VDDSPD VDD/VDDQ VREF VSS VDDID
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D15 VREF: SDRAMs D0 - D15 VSS: SDRAMs D0 - D15 Strap: see Note 1
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D8
DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SCL SAD SA0 SA1 SA2 VSS
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD A0 A1 A2 WP
D4
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
E0
MPBD1031
Figure 3 Note:
Block Diagram UDIMM Raw Card B (x64, 2 Ranks, x8) Table 8 Clock Input CK0, CK0 CK1, CK1 CK2, CK2 Clock Signal Loads Number of SDRAMs 4 SDRAMs 6 SDRAMs 6 SDRAMs Note -- -- --
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 3 5 %
Data Sheet
13
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1 A0 - An RAS CAS WE CKE0 S0 DM0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
BA0 - BA1: SDRAMs D0 - D8 A0 - An: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8
VDDSPD VDD/VDDQ VREF VSS VDDID
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D8 VREF: SDRAMs D0 - D8 VSS: SDRAMs D0 - D8 Strap: see Note 1
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
DM3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 SCL SAD SA0 SA1 SA2 VSS
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD A0 A1 A2 WP
D3
DM6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM8 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
D1
D4
D7
D2
D5
D8
E0
MPBD1001
Figure 4 Note:
Block Diagram UDIMM Raw Card A x72, 1Rank, x8, ECC
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 5.1 5 %
Table 9 Clock Input CK0, CK0 CK1, CK1 CK2, CK2
Clock Signal Loads Number of SDRAMs 3 SDRAMs 3 SDRAMs 3 SDRAMs Note -- -- --
Data Sheet
14
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 S0 S1 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDSPD VDD/VDDQ VREF VSS VDDID
BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 CKE:SDRAMs D9 - D17
SCL SAD SA0 SA1 SA2 VSS
SCL SAD A0 A1 A2 WP
E0
DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D0 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D9 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D10 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D11 DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D12 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D4 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D13
CS
CS
CS
CS
D14
CS
CS
CS
CS
D15
CS
CS
CS
CS
D16
CS
CS
D17
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 DM: SDRAMs D0 - D17 Strap: see Note 1
MPBD1021
Figure 5 Note:
Block Diagram UDIMM Raw Card B x72, 2Ranks, x8, ECC
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 5 % 3. BAn, An, RAS, CAS, WE resistors are 3 5 %
Table 10 Clock Input CK0, CK0 CK1, CK1 CK2, CK2
Clock Signal Loads Number of SDRAMs 6 SDRAMs 6 SDRAMs 6 SDRAMs Note -- -- --
Data Sheet
15
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2 CK R = 120 5% DIMM Connector CK DRAM3 4 DRAM Loads
DRAM4 DRAM5
DRAM1
DRAM2 DRAM6 R = 120 5% DIMM Connector Cap.
Cap. 3 DRAM Loads DRAM1 DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
DRAM6
Cap. 2 DRAM Loads DRAM5 DRAM1
Cap. DIMM Connector Cap.
Cap. R = 120 5% Cap.
1 DRAM Loads
Cap. DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
Cap.
Cap. Cap.
Cap.
Figure 6
Clock Net Wiring
Data Sheet
16
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 11 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT -0.5 VIN VDD VDDQ TA TSTG PD IOUT
-1 -1 -1 0 -55 - -
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 12 Parameter Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.5 2.3 2.5 2.3 0 0.49 x 0.5 x Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x V V V V V V V Unit Note/Test Condition 1)
VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage
I/O Termination Voltage (System)
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4)
VTT
VDDQ VDDQ VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VDDQ VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6 V
1.4 --
5)
Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
17
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 12 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ 8) -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 8) VOUT = 0.35 V 8)
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Table 13 Parameter
AC Timing - Absolute Specifications for PC3200 and PC2700 Symbol -5 DDR400B Min. Max. +0.5 +0.6 0.55 0.55 8 12 12 -- -- -- -6 DDR333 Min. -0.7 -0.6 0.45 0.45 -- 7.5 7.5 0.45 0.45 2.2 Max. +0.7 +0.6 0.55 0.55 -- 12 12 -- -- -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit
Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.5 -0.6 0.45 0.45 5 6 7.5
tCK tCK
ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input)
tDH tDS tIPW
0.4 0.4 2.2
Data Sheet
18
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 13 Parameter AC Timing - Absolute Specifications for PC3200 and PC2700 Symbol -5 DDR400B Min. DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Max. -- +0.7 +0.7 1.25 +0.40 +0.50 -6 DDR333 Min. 1.75 -0.7 -0.7 0.75 -- -- Max. -- +0.7 +0.7 1.25 +0.45 +0.55 ns ns ns
2)3)4)5)6)
Unit
Note/ Test Condition 1)
tDIPW tHZ
1.75 -0.7 -0.7 0.75 -- --
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Write preamble setup time Write postamble Write preamble Address and control input setup time
2)3)4)5)7)
tDQSS tDQSQ tQHS
tCK
ns ns ns
2)3)4)5)
TSOPII
2)3)4)5)
TSOPII
2)3)4)5) 2)3)4)5) 2)3)4)5)
tQH DQS input low (high) pulse width (write tDQSL,H tDSS tDSH
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.7 -- -- -- -- -- 0.60 -- -- --
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8 -- -- -- -- -- 0.60 -- -- --
tCK tCK tCK tCK
ns
2)3)4)5)
2)3)4)5)
Mode register set command cycle time tMRD
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPRES tWPST tWPRE tIS
tCK tCK
ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.6 0.7
-- --
0.75 0.8
-- --
ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC
Read preamble period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Data Sheet
0.9 0.40 40 55 70 15 15
1.1 0.60 70E+3 -- -- -- --
0.9 0.40 42 60 72 18 18
1.1 0.60 70E+3 -- -- -- --
tCK tCK
ns ns ns ns ns ns
tRFC tRCD tRP tRAP
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD - tRASmin 19
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 13 Parameter AC Timing - Absolute Specifications for PC3200 and PC2700 Symbol -5 DDR400B Min. Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Max. -- -- -6 DDR333 Min. 12 15 Max. -- -- ns ns
2)3)4)5)
Unit
Note/ Test Condition 1)
tRRD tWR tDAL
10 15
2)3)4)5) 2)3)4)5)11)
tCK
2 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tWTR Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI
tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
IDD Conditions
Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
21
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 14
IDD Specification for HYS[64/72]D[64/128][300/320]HU-5-B
HYS64D128320HU-5-B HYS64D128320GU-5-B HYS72D128320HU-5-B HYS72D128320GU-5-B HYS64D64300HU-5-B HYS64D64300GU-5-B HYS72D64300HU-5-B HYS72D64300GU-5-B Unit Note 1)2)
Product Type
Organization
512MB x64 1 Rank -5
512MB x64 1 Rank -5 Max. 920 1040 40 290 210 130 380 960 1000 2320 46 2920 Typ. 900 990 30 270 170 110 350 900 950 2160 26 2790 Max. 1040 1170 40 320 230 140 420 1080 1130 2610 51 3290
1GB x64 2 Ranks -5 Typ. 1110 1190 50 480 300 190 620 1110 1150 2230 46 2790 Max. 1300 1420 70 580 420 260 750 1340 1380 2700 91 3300
1GB x72 2 Ranks -5 Typ. 1250 1340 50 540 340 220 700 1250 1300 2510 52 3140 Max. 1460 1590 80 650 470 290 850 1500 1550 3030 103 3710 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 3) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
Typ. 800 880 20 240 150 100 310 800 840 1920 23 2480
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
22
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 15
IDD Specification for HYS[64/72]D[64/128][300/320]HU-6-B
HYS64D128320HU-6-B HYS64D128320GU-6-B HYS72D128320HU-6-B HYS72D128320GU-6-B HYS72D64300HU--6-B HYS72D64300GU-6-B HYS64D64300HU-6-B HYS64D64300GU-6-B Unit Note 1)2)
Product Type
Organization
512MB x64 1 Rank -6
512MB x72 1 Rank -6 Max. 840 920 30 240 190 120 330 840 880 2040 46 2600 Typ. 810 860 30 230 150 100 320 770 810 1940 26 2480 Max. 950 1040 40 270 220 140 370 950 990 2300 51 2930
1 GB x64 2 Ranks -6 Typ. 1000 1040 50 400 270 180 560 960 1000 2000 46 2480 Max. 1170 1250 60 480 380 240 660 1170 1210 2370 91 2930
1 GB x72 2 Ranks -6 Typ. 1130 1170 50 450 310 200 630 1080 1130 2250 52 2790 Max. 1310 1400 70 540 430 270 740 1310 1360 2660 103 3290 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
Typ. 720 760 20 200 140 90 280 680 720 1720 23 2200
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
[
Data Sheet
23
Rev. 1.0, 2004-05 10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents
4
Table 16
SPD Contents
SPD Codes for HYS[64/72]D[64/128][300/320]GU-5-B HYS64D128320GU-5-B HYS72D128320GU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 Rev. 1.0, 2004-05 HYS64D64300GU-5-B HYS72D64300GU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 24
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC3200U-30330 Rev 0.0 HEX 80 08 07 0D 0B 01 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 16 SPD Codes for HYS[64/72]D[64/128][300/320]GU-5-B (cont'd) HYS64D128320GU-5-B HYS72D128320GU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 51 C1 00 xx 37 32 44 31 Rev. 1.0, 2004-05 HYS64D64300GU-5-B HYS72D64300GU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 50 C1 00 xx 37 32 44 36
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3F C1 00 xx 36 34 44 31
Label Code JEDEC SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 Description
PC3200U-30330 Rev 0.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3E C1 00 xx 36 34 44 36
tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 -8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4
Data Sheet
25
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 16 SPD Codes for HYS[64/72]D[64/128][300/320]GU-5-B (cont'd) HYS64D128320GU-5-B HYS72D128320GU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 32 38 33 32 30 47 55 35 42 20 20 20 20 20 0x xx xx xx xx 00 Rev. 1.0, 2004-05 HYS64D64300GU-5-B HYS72D64300GU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 34 33 30 30 47 55 35 42 20 20 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 32 38 33 32 30 47 55 35 42 20 20 20 20 20 0x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC3200U-30330 Rev 0.0 HEX 34 33 30 30 47 55 35 42 20 20 20 20 20 20 0x xx xx xx xx 00
99 - 127 not used
Data Sheet
26
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[64/128][300/320]HU-5-B HYS64D128320HU-5-B HYS72D128320HU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50 Rev. 1.0, 2004-05 HYS64D64300HU-5-B HYS72D64300HU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 50 75 50
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC3200U-30330 Rev 0.0 HEX 80 08 07 0D 0B 01 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02 20 C1 60 50 75 50
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns]
Data Sheet
27
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU-5-B (cont'd) HYS64D128320HU-5-B HYS72D128320HU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 51 C1 00 xx 37 32 44 31 32 Rev. 1.0, 2004-05 HYS64D64300HU-5-B HYS72D64300HU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 50 C1 00 xx 37 32 44 36 34
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3F C1 00 xx 36 34 44 31 32
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 77 Description
PC3200U-30330 Rev 0.0 HEX 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 00 00 00 3E C1 00 xx 36 34 44 36 34
tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5
Data Sheet
28
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU-5-B (cont'd) HYS64D128320HU-5-B HYS72D128320HU-5-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 48 55 35 42 20 20 20 20 20 0x xx xx xx xx 00 Rev. 1.0, 2004-05 HYS64D64300HU-5-B HYS72D64300HU-5-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 33 30 30 48 55 35 42 20 20 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 48 55 35 42 20 20 20 20 20 0x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC3200U-30330 Rev 0.0 HEX 33 30 30 48 55 35 42 20 20 20 20 20 20 0x xx xx xx xx 00
99 - 127 not used
Data Sheet
29
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for HYS[64/72]D[64/128][300/320]GU-6-B HYS64D128320GU-6-B HYS72D128320GU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1 75 70 00 00 Rev. 1.0, 2004-05 HYS64D64300GU-6-B HYS72D64300GU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1 75 70 00 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC2700U-25330 Rev 0.0 HEX 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns]
Data Sheet
30
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 18 SPD Codes for HYS[64/72]D[64/128][300/320]GU-6-B (cont'd) HYS64D128320GU-6-B HYS72D128320GU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 55 C1 00 xx 37 32 44 31 32 Rev. 1.0, 2004-05 HYS64D64300GU-6-B HYS72D64300GU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 54 C1 00 xx 37 32 44 36 34
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 43 C1 00 xx 36 34 44 31 32
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 77 Description
PC2700U-25330 Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 42 C1 00 xx 36 34 44 36 34
tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5
Data Sheet
31
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 18 SPD Codes for HYS[64/72]D[64/128][300/320]GU-6-B (cont'd) HYS64D128320GU-6-B HYS72D128320GU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 47 55 36 42 20 20 20 20 20 0x xx xx xx xx 00 Rev. 1.0, 2004-05 HYS64D64300GU-6-B HYS72D64300GU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 33 30 30 47 55 36 42 20 20 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 47 55 36 42 20 20 20 20 20 0x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC2700U-25330 Rev 0.0 HEX 33 30 30 47 55 36 42 20 20 20 20 20 20 0x xx xx xx xx 00
99 - 127 not used
Data Sheet
32
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for HYS[64/72]D[64/128][300/320]HU-6-B HYS64D128320HU-6-B HYS72D128320HU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1 75 70 00 00 Rev. 1.0, 2004-05 HYS64D64300HU-6-B HYS72D64300HU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C1 75 70 00 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
PC2700U-25330 Rev 0.0 HEX 80 08 07 0D 0B 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns]
Data Sheet
33
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 19 SPD Codes for HYS[64/72]D[64/128][300/320]HU-6-B HYS64D128320HU-6-B HYS72D128320HU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 55 C1 00 xx 37 32 44 31 32 Rev. 1.0, 2004-05 HYS64D64300HU-6-B HYS72D64300HU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 54 C1 00 xx 37 32 44 36 34
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 43 C1 00 xx 36 34 44 31 32
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 77 Description
PC2700U-25330 Rev 0.0 HEX 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 00 00 42 C1 00 xx 36 34 44 36 34
tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5
Data Sheet
34
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
SPD Contents Table 19 SPD Codes for HYS[64/72]D[64/128][300/320]HU-6-B HYS64D128320HU-6-B HYS72D128320HU-6-B 1 GByte x72 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 48 55 36 42 20 20 20 20 20 0x xx xx xx xx 00 Rev. 1.0, 2004-05 HYS64D64300HU-6-B HYS72D64300HU-6-B 512 MB x72 1 Rank (x8) Rev 0.0 HEX 33 30 30 48 55 36 42 20 20 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
512 MB x64 1 Rank (x8)
1 GByte x64 2 Ranks (x8) Rev 0.0 HEX 38 33 32 30 48 55 36 42 20 20 20 20 20 0x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC2700U-25330 Rev 0.0 HEX 33 30 30 48 55 36 42 20 20 20 20 20 20 0x xx xx xx xx 00
99 - 127 not used
Data Sheet
35
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 2.7 MAX. A 0.15 A B C
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-32
Figure 7
Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module)
Data Sheet
36
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 8 Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module)
L-DIM-184-30
Data Sheet
37
Rev. 1.0, 2004-05
17.8
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-33
Figure 9
Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module)
Data Sheet
38
Rev. 1.0, 2004-05
17.8
HYS[64/72]D[64300/128320][G/H]U-[5/6]-B Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-DIM-184-31
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 10 Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7/-B (2 Rank Module)
Data Sheet
39
Rev. 1.0, 2004-05
www.infineon.com
Published by Infineon Technologies AG

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